5#ifndef ATMEGA2560_DEFINITIONS_ATMEGA2560_H
6#define ATMEGA2560_DEFINITIONS_ATMEGA2560_H
ADC channels, multiplexer selections, references and modes.
Analog comparator input and interrupt definitions.
Boot section sizes and Flash address ranges.
Core register and status flags.
Clock sources, oscillator and CPU prescaler.
Device, package and operating-grade selection.
Device identity and peripheral counts.
EEPROM organization and endurance.
Operating conditions and absolute maximum ratings.
Datasheet revision and device silicon errata references.
External interrupt and pin-change mappings.
Low, high, and extended fuse bit locations.
GPIO port widths, masks and pull-ups.
Interrupt vector sources, slot numbers and word addresses.
JTAG debug and boundary-scan interface.
Memory protection and bootloader lock bit positions.
Flash, EEPROM, SRAM, and external-memory geometry.
PWM output channels and associated logical pins.
Physical terminal and ball mappings for 100-terminal packages.
Supported package types and selected package.
Pin capabilities and alternate function identifiers.
Logical GPIO pin and port identifiers.
Sleep modes and peripheral power gates.
In-system programming interface, signatures and page geometry.
Capacitive touch software support metadata.
Asynchronous Timer2 real-time counter support.
Register bit positions and field masks.
Data-space addresses of ATmega2560 peripheral registers.
Reset origins and status.
SPI interface and pin definitions.
Two-wire serial interface characteristics.
Timer/counter architecture and modes.
USART frame modes, channel numbers and pin multiplexing.
Watchdog oscillator and timeout selections.
External memory interface buses and control registers.
1.15.0